Contemporary image sensors employ 4T pixel array implementing correlated double sampling (CDS) and column parallel analog to digital converter (ADC) structures, usually based on ramp based time to digital implementations. Each column in this case contains (besides the digital register/counter) a comparator that records the cross of the sampled voltage (reset or exposure value) with a ramp voltage that is common to all columns.
There is a growing need to reduce the size and cost of pixels and ADC structures.